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<strong>About The Job<br><br></strong><strong>Mercor</strong> connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include <strong>Benchmark</strong>, <strong>General Catalyst</strong>, <strong>Peter Thiel</strong>, <strong>Adam D'Angelo</strong>, <strong>Larry Summers</strong>, and <strong>Jack Dorsey</strong>.<br><br><strong>Position:</strong> RTL Design Engineers<br><br><strong>Type:</strong> <strong>Contract<br><br></strong><strong>Compensation:</strong> <strong>$100–$175/hour<br><br></strong><strong>Location:</strong> <strong>Remote<br><br></strong><strong>Duration:</strong> <strong>3+ months<br><br></strong><strong>Commitment:</strong> <strong>40 hours/week<br><br></strong><strong>Role Responsibilities<br><br></strong><ul><li>Evaluate digital chip design workflows to enhance AI model training and evaluation.</li><li>Design and verify RTL components using Verilog/SystemVerilog.</li><li>Collaborate with architecture, verification, and implementation teams to improve model outputs.</li><li>Develop reusable verification components and testbench infrastructure.</li><li>Leverage LLM-based tools to accelerate chip design and verification processes.</li><li>Work independently and asynchronously to meet project deadlines.<br><br><br></li></ul><strong>Qualifications<br><br></strong><strong>Must-Have<br><br></strong><ul><li>3–10 years of experience in digital RTL design or design verification.</li><li>Strong proficiency in Verilog/SystemVerilog and UVM.</li><li>Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.</li><li>Experience with ASIC design flows and common EDA tools.</li><li>Ability to write clear design documentation and communicate technical tradeoffs.<br><br><br></li></ul><strong>Preferred<br><br></strong><ul><li>Knowledge of AMBA protocols (AXI, AHB, APB).</li><li>Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.</li><li>Exposure to formal verification or SV/UVM-based design verification.<br><br><br></li></ul><strong>Start Date<br><br></strong><ul><li>Week of 04/23; applications reviewed on a rolling basis.<br><br><br></li></ul><strong>Compensation & Legal<br><br></strong><ul><li>Hourly contractor, Paid weekly.<br><br><br></li></ul><strong>Application Process (Takes 20–30 mins to complete)<br><br></strong><ul><li>Upload resume</li><li>AI interview based on your resume</li><li>Submit form<br><br><br></li></ul><strong>Resources & Support<br><br></strong><ul><li>For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome</li><li>For any help or support, reach out to: support@mercor.com<br><br><br></li></ul><em>PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.</em>
